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Performance analysis of a scalable hardware FPGA Skein implementation.

機(jī)譯：可擴(kuò)展的硬件FPGA Skein實(shí)現(xiàn)的性能分析。

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Hashing functions are a key cryptographic primitive used in many everyday applications, such as authentication, ensuring data integrity, as well as digital signatures. The current hashing standard is defined by the National Institute of Standards and Technology (NIST) as the Secure Hash Standard (SHS), and includes SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512. SHS's level of security is waning as technology and analysis techniques continue to develop over time. As a result, after the 2005 Cryptographic Hash Workshop, NIST called for the creation of a new cryptographic hash algorithm to replace SHS. The new candidate algorithms were submitted on October 31st, 2008, and of them fourteen have advanced to round two of the competition. The competition is expected to produce a final replacement for the SHS standard by 2012.;Multi-core processors, and parallel programming are the dominant force in computing, and some of the new hashing algorithms are attempting to take advantage of these resources by offering parallel tree-hashing variants to the algorithms. Tree-hashing allows multiple parts of the data on the same level of a tree to be operated on simultaneously, resulting in the potential to reduce the execution time complexity for hashing from O(n) to O(log n). Designs for tree-hashing require that the scalability and parallelism of the algorithms be researched on all platforms, including multi-core processors (CPUs), graphics processors (GPUs), as well as custom hardware (ASICs and FPGAs). Skein, the hashing function that this work has focused on, offers a tree-hashing mode with different options for the maximum tree height, and leaf node size, as well as the node fan-out.;This research focuses on creating and analyzing the performance of scalable hardware designs for Skein's tree hashing mode. Different ideas and approaches on how to modify sequential hashing cores, and create scalable control logic in order to provide for highspeed and low-area parallel hashing hardware are presented and analyzed. Equations were created to help understand the expected performance and potential bottlenecks of Skein in FPGAs. The equations are intended to assist the decision making process during the design phase, as well as potentially provide insight into design considerations for other tree hashing schemes in FPGAs. The results are also compared to current sequential designs of Skein, providing a complete analysis of the performance of Skein in an FPGA.
機(jī)譯：散列函數(shù)是許多日常應(yīng)用中使用的關(guān)鍵加密原語，例如身份驗(yàn)證，確保數(shù)據(jù)完整性以及數(shù)字簽名。美國(guó)國(guó)家標(biāo)準(zhǔn)技術(shù)研究所（NIST）將當(dāng)前的哈希標(biāo)準(zhǔn)定義為安全哈希標(biāo)準(zhǔn)（SHS），其中包括SHA-1，SHA-224，SHA-256，SHA-384和SHA-512。隨著技術(shù)和分析技術(shù)的不斷發(fā)展，SHS的安全級(jí)別正在下降。結(jié)果，在2005年加密哈希研討會(huì)之后，NIST呼吁創(chuàng)建一種新的加密哈希算法來代替SHS。新的候選算法已于2008年10月31日提交，其中14項(xiàng)已進(jìn)入競(jìng)賽的第二輪。預(yù)計(jì)該競(jìng)爭(zhēng)將在2012年之前最終替代SHS標(biāo)準(zhǔn)。多核處理器和并行編程是計(jì)算的主導(dǎo)力量，并且一些新的哈希算法試圖通過提供并行來利用這些資源。算法的樹形哈希變體。樹哈希允許同時(shí)操作樹的同一級(jí)別上的數(shù)據(jù)的多個(gè)部分，從而有可能降低哈希從O（n）到O（log n）的執(zhí)行時(shí)間復(fù)雜度。散列樹設(shè)計(jì)要求在所有平臺(tái)上研究算法的可伸縮性和并行性，包括多核處理器（CPU），圖形處理器（GPU）以及定制硬件（ASIC和FPGA）。 Skein是這項(xiàng)工作重點(diǎn)關(guān)注的哈希函數(shù)，它提供了一種樹哈希模式，該模式具有最大樹高，葉節(jié)點(diǎn)大小以及節(jié)點(diǎn)扇出的不同選項(xiàng)。 Skein的樹哈希模式的可伸縮硬件設(shè)計(jì)的性能。提出并分析了有關(guān)如何修改順序哈希核心以及創(chuàng)建可伸縮控制邏輯以提供高速和低區(qū)域并行哈希硬件的不同思想和方法。創(chuàng)建了公式來幫助理解FPGA中Skein的預(yù)期性能和潛在瓶頸。這些方程式旨在協(xié)助設(shè)計(jì)階段的決策過程，并可能提供有關(guān)FPGA中其他樹形哈希方案的設(shè)計(jì)考慮因素的見解。還將結(jié)果與Skein的當(dāng)前順序設(shè)計(jì)進(jìn)行了比較，從而提供了FPGA中Skein性能的完整分析。

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  • 作者

    Schorr, Aric.;

  • 作者單位

    Rochester Institute of Technology.;

  • 授予單位 Rochester Institute of Technology.;
  • 學(xué)科 Engineering Computer.
  • 學(xué)位 M.S.
  • 年度 2010
  • 頁碼 71 p.
  • 總頁數(shù) 71
  • 原文格式 PDF
  • 正文語種 eng
  • 中圖分類 公共建筑;
  • 關(guān)鍵詞

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