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Solving complex modeling of system-on-a-chip (SOC) test automation and optimal resource allocation by neural networks.

機(jī)譯：通過神經(jīng)網(wǎng)絡(luò)解決復(fù)雜的系統(tǒng)級(jí)芯片（SOC）測(cè)試自動(dòng)化建模和最佳資源分配問題。

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摘要

In this research, we investigate the methods for solving the complex modeling of System-on-a-Chip (SOC) test automation. In the semiconductor industry, a new system design, called System-on-a-Chip (SOC) design, is currently being introduced to use multiple embedded modules built on a single chip. With today's technology, a single chip can consist of millions of transistors or components. To design a SOC system on a single chip, a designer often uses pre-designed, reusable megacells known as cores in the SOC design. Embedded the cores onto SOC increases width of the system bus and thus increases overall system performance, i.e., it can offer higher speed and lower power consumption on SOC chips.; The objective of this research is to optimize the testing time and the test resource allocation for System-on-a-Chip (SOC). The mathematic formulation and the neural networks with different techniques are proposed to solve these SOC test problems. The objective of this SOC test automation is to minimize the SOC testing time subject to different constraints: (i) precedence constraint, (ii) test resource constraint, (iii) core constraint, and (iv) power constraint. Heuristic algorithms are used to help the neural network avoid getting trapped in a local optimal. The developed neural networks can effectively solve the SOC test scheduling models with disjunctive constraints. The proposed maximum neural network can be used to solve NP-hard SOC test problems within polynomial time. The results show that it is possible to find the optimal SOC testing time of the complex SOC systems with shorter computation time than the existing traditional methods. The techniques presented in this research can be used in the test automation for System-on-a-Chip (SOC) design.
機(jī)譯：在這項(xiàng)研究中，我們研究解決片上系統(tǒng)（SOC）測(cè)試自動(dòng)化的復(fù)雜建模的方法。在半導(dǎo)體行業(yè)，目前正在引入一種稱為片上系統(tǒng)（SOC）設(shè)計(jì)的新系統(tǒng)設(shè)計(jì)，以使用在單個(gè)芯片上構(gòu)建的多個(gè)嵌入式模塊。利用當(dāng)今的技術(shù)，單個(gè)芯片可以包含數(shù)百萬(wàn)個(gè)晶體管或組件。為了在單個(gè)芯片上設(shè)計(jì)SOC系統(tǒng)，設(shè)計(jì)人員通常使用預(yù)先設(shè)計(jì)的可重復(fù)使用的巨型電池，在SOC設(shè)計(jì)中稱為 core 。將內(nèi)核嵌入到SOC中可以增加系統(tǒng)總線的寬度，從而提高整體系統(tǒng)性能，即，可以在SOC芯片上提供更高的速度和更低的功耗。這項(xiàng)研究的目的是優(yōu)化片上系統(tǒng)（SOC）的測(cè)試時(shí)間和測(cè)試資源分配。為了解決這些SOC測(cè)試問題，提出了采用不同技術(shù)的數(shù)學(xué)公式和神經(jīng)網(wǎng)絡(luò)。此SOC測(cè)試自動(dòng)化的目標(biāo)是最大程度地減少受到不同約束的SOC測(cè)試時(shí)間：（i）優(yōu)先約束，（ii）測(cè)試資源約束，（iii）核心約束和（iv）功率約束）。啟發(fā)式算法用于幫助神經(jīng)網(wǎng)絡(luò)避免陷入局部最優(yōu)狀態(tài)。所開發(fā)的神經(jīng)網(wǎng)絡(luò)可以有效地解決具有分離約束的SOC測(cè)試調(diào)度模型。所提出的最大神經(jīng)網(wǎng)絡(luò)可用于解決多項(xiàng)式時(shí)間內(nèi)的NP-hard SOC測(cè)試問題。結(jié)果表明，與現(xiàn)有的傳統(tǒng)方法相比，可以以更短的計(jì)算時(shí)間找到復(fù)雜SOC系統(tǒng)的最優(yōu)SOC測(cè)試時(shí)間。這項(xiàng)研究中介紹的技術(shù)可以用于片上系統(tǒng)（SOC）設(shè)計(jì)的測(cè)試自動(dòng)化中。

著錄項(xiàng)

  • 作者

    Kloypayan, Jirawan.;

  • 作者單位

    North Carolina State University.;

  • 授予單位 North Carolina State University.;
  • 學(xué)科 Engineering Industrial.
  • 學(xué)位 Ph.D.
  • 年度 2002
  • 頁(yè)碼 101 p.
  • 總頁(yè)數(shù) 101
  • 原文格式 PDF
  • 正文語(yǔ)種 eng
  • 中圖分類 一般工業(yè)技術(shù);
  • 關(guān)鍵詞

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