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Low voltage circuit design techniques for cubic-millimeter computing.

機(jī)譯：用于立方毫米計(jì)算的低壓電路設(shè)計(jì)技術(shù)。

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Cubic-millimeter computers complete with microprocessors, memories, sensors, radios and power sources are becomingly increasingly viable. Power consumption is one of the last remaining barriers to cubic-millimeter computing and is the subject of this work. In particular, this work focuses on minimizing power consumption in digital circuits using low voltage operation.;Chapter 2 includes a general discussion of low voltage circuit behavior, specifically that at subthreshold voltages. In Chapter 3, the implications of transistor scaling on subthreshold circuits are considered. It is shown that the slow scaling of gate oxide relative to the device channel length leads to a 60% reduction in Ion/Ioff between the 90nm and 32nm nodes, which results in sub-optimal static noise margins, delay, and power consumption. It is also shown that simple modifications to gate length and doping can alleviate some of these problems.;Three low voltage test-chips are discussed for the remainder of this work. The first test-chip implements the Subliminal Processor (Chapter 4), a sub-200mV 8-bit microprocessor fabricated in a 0.13mum technology. Measurements first show that the Subliminal Processor consumes only 3.5pJ/instruction at Vdd=350mV. Measurements of 20 dies then reveal that proper body biasing can eliminate performance variations and reduce mean energy substantially at low voltage. Finally, measurements are used to explore the effectiveness of body biasing, voltage scaling, and various gate sizing techniques for improving speed.;The second test-chip implements the Phoenix Processor (Chapter 5), a low voltage 8-bit microprocessor optimized for minimum power operation in standby mode. The Phoenix Processor was fabricated in a 0.18mum technology in an area of only 915x915mum2. The aggressive standby mode strategy used in the Phoenix Processor is discussed thoroughly. Measurements at Vdd=0.5V show that the test-chip consumes 226nW in active mode and only 35.4pW in standby mode, making an on-chip battery a viable option.;Finally, the third test-chip implements a low voltage image sensor (Chapter 6). A 128x128 image sensor array was fabricated in a 0.13mum technology. Test-chip measurements reveal that operation below 0.6V is possible with power consumption of only 1.9muW at 0.6V. Extensive characterization is presented with specific emphasis on noise characteristics and power consumption.
機(jī)譯：配備有微處理器，存儲(chǔ)器，傳感器，無(wú)線電和電源的立方毫米計(jì)算機(jī)正變得越來越可行。功耗是立方毫米計(jì)算剩下的最后障礙之一，也是這項(xiàng)工作的主題。特別地，這項(xiàng)工作著重于使用低壓操作使數(shù)字電路中的功耗最小化。第二章對(duì)低壓電路的性能進(jìn)行了一般性討論，特別是在低于閾值電壓下。在第3章中，考慮了晶體管縮放對(duì)亞閾值電路的影響。結(jié)果表明，柵極氧化物相對(duì)于器件溝道長(zhǎng)度的緩慢縮放會(huì)導(dǎo)致90nm和32nm節(jié)點(diǎn)之間的Ion / Ioff降低60％，從而導(dǎo)致靜態(tài)噪聲裕度，延遲和功耗都不理想。還顯示出對(duì)柵極長(zhǎng)度和摻雜的簡(jiǎn)單修改可以緩解其中的一些問題。在本工作的其余部分中，將討論三個(gè)低壓測(cè)試芯片。第一個(gè)測(cè)試芯片實(shí)現(xiàn)了Subliminal Processor（第4章），Subliminal Processor是用0.13mum技術(shù)制造的低于200mV的8位微處理器。測(cè)量首先顯示，在Vdd = 350mV時(shí)，Subliminal處理器僅消耗3.5pJ /指令。然后對(duì)20個(gè)芯片進(jìn)行測(cè)量，發(fā)現(xiàn)適當(dāng)?shù)钠秒妷嚎梢韵阅懿町悾⒃诘碗妷合麓蠓档推骄芰?。最后，通過測(cè)量來探索體偏置，電壓縮放和各種柵極尺寸調(diào)整技術(shù)的有效性，以提高速度;第二個(gè)測(cè)試芯片實(shí)現(xiàn)了Phoenix處理器（第5章），這是針對(duì)最小化而優(yōu)化的低壓8位微處理器待機(jī)模式下的電源操作。 Phoenix處理器采用0.18mum技術(shù)制造，面積僅為915x915mum2。徹底討論了Phoenix處理器中使用的積極待機(jī)模式策略。在Vdd = 0.5V的測(cè)量結(jié)果表明，測(cè)試芯片在活動(dòng)模式下的功耗為226nW，在待機(jī)模式下僅為35.4pW，這使得片上電池成為可行的選擇。最后，第三個(gè)測(cè)試芯片實(shí)現(xiàn)了低壓圖像傳感器（第6章）。 128x128的圖像傳感器陣列采用0.13mm技術(shù)制造。測(cè)試芯片的測(cè)量結(jié)果表明，在0.6V以下工作時(shí)，只有0.6μV的功耗才可能達(dá)到1.9μW。提出了廣泛的表征，特別強(qiáng)調(diào)了噪聲特性和功耗。

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  • 作者

    Hanson, Scott McLean.;

  • 作者單位

    University of Michigan.;

  • 授予單位 University of Michigan.;
  • 學(xué)科 Engineering Electronics and Electrical.
  • 學(xué)位 Ph.D.
  • 年度 2009
  • 頁(yè)碼 125 p.
  • 總頁(yè)數(shù) 125
  • 原文格式 PDF
  • 正文語(yǔ)種 eng
  • 中圖分類 無(wú)線電電子學(xué)、電信技術(shù);
  • 關(guān)鍵詞

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