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首頁> 外文學(xué)位 >An N-bit multicell-encoded cellular neural network for multidata processing.

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An N-bit multicell-encoded cellular neural network for multidata processing.

機譯：用于多數(shù)據(jù)處理的N位多單元編碼的細胞神經(jīng)網(wǎng)絡(luò)。

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Significant disadvantages of Cellular Neural Networks (CNNs) include the implementation of very large CNN arrays and the time required for loading/unloading the CNN data. This research addresses both of these problems by developing a new CNN architecture for processing the data of multiple CNN cells simultaneously. Several significant contributions of this research include a mathematical formalism for this new CNN, a CMOS implementation of a specific test architecture, and the design of the equivalent test architecture using predominately Quantum-Well Device (QWD) circuits.;For a digital CNN with n bits per cell, this new architecture is an n-Bit Multi-Cell Encoded Cellular Neural (nB-MCE CNN). The specific test architecture selected for in-depth investigation is a 1B-4CE CNN which processes the data of four 1B CNN cells simultaneously. A mathematical description of the 1B-4CE CNN templates and a mathematical expression of the 1B-4CE CNN dynamics in terms of 1B-4CE CNN variables and newly defined 1B-4CE CNN templates is presented. System-level simulations for both for both Connected-Component Detection (CCD) cases and Edge Detection cases validate this new CNN architecture.;A CMOS implementation of a 1B-4CE CNN system is presented, including the design and operation of the circuits and functional blocks of this system. Experimental results of a one-dimensional 1B-4CE-CNN CMOS chip are presented for CCD cases and Edge Detection cases using both one-chip and two-chip systems. These test results indicate the correct encoding, processing and decoding of single-data CNN cells from multiple 1B-4CE cell components and between 1B-4CE CNN cells.;A 1B-4CE CNN is also designed and simulated using predominately QWDs. Mathematical models for several QWDs, including the multiple-gated Resonant Tunneling Diode (mgRTD), are developed. A general mgRTD comparator is analyzed in detail using the mgRTD model presented. This comparator is then customized to meet the specific requirements of many of the required 1B-4CE CNN functional blocks. System-level simulations of this QWD-based 1B-4CE-CNN for both CCD test cases and Edge Detection test cases match the expected 4B encoded and 1B decoded outputs at operating speeds at 4GHz. These simulation results demonstrate the compatibility of this new, advanced CNN with a futuristic device technology.

機譯：蜂窩神經(jīng)網(wǎng)絡(luò)（CNN）的重大缺點包括非常大的CNN陣列的實現(xiàn)以及加載/卸載CNN數(shù)據(jù)所需的時間。這項研究通過開發(fā)新的CNN架構(gòu)同時處理多個CNN單元的數(shù)據(jù)來解決這兩個問題。這項研究的一些重要貢獻包括針對此新CNN的數(shù)學(xué)形式化，特定測試架構(gòu)的CMOS實現(xiàn)以及主要使用量子阱器件（QWD）電路的等效測試架構(gòu)的設(shè)計。每單元1位元，這種新架構(gòu)是n位多單元編碼細胞神經(jīng)網(wǎng)絡(luò)（nB-MCE CNN）。選擇用于深入研究的特定測試體系結(jié)構(gòu)是1B-4CE CNN，它可以同時處理四個1B CNN單元的數(shù)據(jù)。提供了1B-4CE CNN模板的數(shù)學(xué)描述以及1B-4CE CNN變量和新定義的1B-4CE CNN模板的1B-4CE CNN動力學(xué)的數(shù)學(xué)表達式。針對連接組件檢測（CCD）案例和邊緣檢測案例的系統(tǒng)級仿真驗證了這種新的CNN體??系結(jié)構(gòu)。；提出了1B-4CE CNN系統(tǒng)的CMOS實現(xiàn)，包括電路的設(shè)計和操作以及功能該系統(tǒng)的塊。一維1B-4CE-CNN CMOS芯片的實驗結(jié)果針對使用單芯片和兩芯片系統(tǒng)的CCD情況和邊緣檢測情況進行了介紹。這些測試結(jié)果表明了來自多個1B-4CE單元組件以及1B-4CE CNN單元之間的單數(shù)據(jù)CNN單元的正確編碼，處理和解碼。還設(shè)計了一個1B-4CE CNN，并使用了主要的QWD對它們進行了仿真。開發(fā)了幾種QWD的數(shù)學(xué)模型，包括多門諧振隧道二極管（mgRTD）。使用提供的mgRTD模型詳細分析了一般的mgRTD比較器。然后定制該比較器，以滿足許多所需的1B-4CE CNN功能塊的特定要求?；贑CD的測試案例和邊緣檢測測試案例的基于QWD的1B-4CE-CNN的系統(tǒng)級仿真以4 GHz的工作速度與預(yù)期的4B編碼和1B解碼輸出匹配。這些仿真結(jié)果證明了這種新的，先進的CNN與未來派設(shè)備技術(shù)的兼容性。

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作者
Villareal, Samuel S.;
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作者單位

Texas A&M University.;

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授予單位 Texas A&M University.;
學(xué)科 Engineering Electronics and Electrical.
學(xué)位 Ph.D.
年度 1999
頁碼 254 p.
總頁數(shù) 254
原文格式 PDF
正文語種 eng
中圖分類
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An N-bit multicell-encoded cellular neural network for multidata processing.

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