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Quadratic programming based framework for high-level area estimation and performance-driven placement for asics.

機譯：基于二次編程的框架，用于高級區(qū)域估算和asics的性能驅(qū)動放置。

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The work presented here explores the application of quadratic programming based optimization techniques to two major areas of VLSI CAD domain namely, (i) performance driven placement and (ii) area estimation after high-level synthesis. The quadratic programming technique is a very fast method and it also results in high quality solutions.; With the increasing complexity of present-day integrated circuits, there is a need for fast layout generation algorithms that are driven by performance constraints such as timing and clocking. We model the placement problem as a quadratic optimization problem and suggest techniques for incorporating the performance constraints. The performance constraints that we consider for the placement problem are timing and clocking. The timing driven placement computes the net delay bounds and guides the placement problem under the timing constraints. Also, techniques for minimizing the critical path delay have been incorporated into the model. The clock-skew minimization problem attempts to generate a zero-skew routing for the clock signal while minimizing performance costs. While addressing the clock-skew minimization problem, a new clock-routing tree has been proposed which is well suited for routing the clock signal in row-based design styles.; One of the main objectives of placement algorithms is to minimize the overall area of an IC chip. The overall area depends on the logic module area as well as the wiring area. The latter can be found exactly after completion of routing. Thus placement algorithms can only estimate the routing cost. As part of this research we study the validity of the metrics used for the estimation of quality of placement.; The layout area estimation problem is addressed by first computing a Quadratic Programming based floorplan for the given RTL design. The resulting floorplan is then processed through a topological floorplanner to minimize the layout area. The area estimates are then computed using Steiner tree based routing estimation heuristics.; All of the above techniques have been tested on a number of benchmark examples and the experimental results confirm the effectiveness of the proposed techniques.
機譯：本文介紹的工作探索了基于二次編程的優(yōu)化技術(shù)在VLSI CAD域的兩個主要領(lǐng)域中的應(yīng)用，即（i）性能驅(qū)動的放置和（ii）高級綜合后的面積估計。二次編程技術(shù)是一種非?？焖俚姆椒?，它還可以提供高質(zhì)量的解決方案。隨著當(dāng)今集成電路的復(fù)雜性增加，需要由諸如時序和時鐘之類的性能約束所驅(qū)動的快速布局生成算法。我們將布局問題建模為二次優(yōu)化問題，并提出合并性能約束的技術(shù)。對于布局問題，我們考慮的性能約束是時序和時鐘。時序驅(qū)動的布局計算凈延遲邊界，并在時序約束下指導(dǎo)布局問題。而且，用于使關(guān)鍵路徑延遲最小化的技術(shù)已被納入模型。時鐘偏移最小化問題試圖在使性能成本最小化的同時為時鐘信號生成零偏移路由。在解決時鐘偏移最小化問題時，已經(jīng)提出了一種新的時鐘路由樹，該樹非常適合以基于行的設(shè)計樣式路由時鐘信號。布局算法的主要目標(biāo)之一是最小化IC芯片的整體面積?？偯娣e取決于邏輯模塊面積以及接線面積。后者可以在路由完成后找到。因此，放置算法只能估算布線成本。作為這項研究的一部分，我們研究了用于評估展示位置質(zhì)量的指標(biāo)的有效性。通過首先為給定的RTL設(shè)計計算基于二次規(guī)劃的布局圖，可以解決布局面積估計問題。然后，通過拓?fù)淦矫嬉?guī)劃器處理生成的平面布置圖，以最小化布局面積。然后使用基于斯坦納樹的路由估計啟發(fā)法來計算面積估計。所有上述技術(shù)已在多個基準(zhǔn)示例上進(jìn)行了測試，實驗結(jié)果證實了所提出技術(shù)的有效性。

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