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Efficient and Quality Assured Techniques for Analog Circuit Design Automation

機(jī)譯：模擬電路設(shè)計自動化的高效和質(zhì)量保證技術(shù)

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Automating the designs of analog and mixed signal circuits is challenging because circuit designs are heuristics intensive and the performance evaluations are expensive. This dissertation addresses multiple strategies to enhance the quality and efficiency of the circuit design automation. With comparing various global optimization solvers such as Evolutionary Algorithm (EA), Simulated Annealing (SA) and Genetic Algorithms (GA), we introduce Random Region Covering (RRC) method as our global optimizer. RRC explores the landscape by initiating local optimization solvers with multiple random starting points. The optimization quality improves as the number of starting points increases. We propose Random Region Covering Theory (RRCT) theory to explain why this technique is efficient at searching for the global optimum. In addition to analyzing the efficiency of the RRC, the theory gives a probability-based estimation of the goodness of the optimization result. Quantifying the goodness of the current design has two advantages. First, we can estimate the improvement margin of the candidate design. In this case, we can avoid extra costs associated with over-optimizing a qualified design. Second, we can estimate the cost of achieving the design goal which provides a sound termination condition to the optimization flow. To enhance the efficiency, an optimization scheme should either speed up the circuit simulation or invoke the high-cost circuit simulator as little as possible. A common technique to improve circuit simulation efficiency is to replace the transistor level model with a behavior level model. However, the accuracy of equation-based or knowledge-based behavioral models is problem dependent. For new circuit topologies, these methods have to develop fitted mathematical models which are time consuming and difficult, particularly with respect to Process, Voltage and Temperature (PVT) variations. Instead of directly applying a numerical optimization algorithm to full transistor-level response surface, it is more efficient to apply the optimization to a surrogate model trained by an iteratively updated, high-fidelity simulation database. The accuracy of the surrogate model becomes the key to achieving high quality optimization results. This dissertation proposes a novel optimization scheme with combining the advantages of Gaussian process (GP) model with RRC optimizer. We perform experiments to compare the proposed technique with well-known Bayesian Optimization (BO) methods. The results proved the effectiveness of the proposed method. The DesignEasy software was developed to implement the above functions and to provide a general User Interface (UI) for circuit design automation.
機(jī)譯：模擬和混合信號電路的設(shè)計自動化是具有挑戰(zhàn)性的，因?yàn)殡娐吩O(shè)計需要大量的試探法，而性能評估也很昂貴。本文提出了多種提高電路設(shè)計自動化質(zhì)量和效率的策略。通過比較各種全局優(yōu)化求解器，例如進(jìn)化算法（EA），模擬退火（SA）和遺傳算法（GA），我們引入了隨機(jī)區(qū)域覆蓋（RRC）方法作為我們的全局優(yōu)化器。 RRC通過啟動具有多個隨機(jī)起點(diǎn)的局部優(yōu)化求解器來探索環(huán)境。隨著起點(diǎn)數(shù)量的增加，優(yōu)化質(zhì)量也會提高。我們提出隨機(jī)區(qū)域覆蓋理論（RRCT）理論來解釋為什么這種技術(shù)在尋找全局最優(yōu)值時很有效。除了分析RRC的效率外，該理論還對優(yōu)化結(jié)果的優(yōu)劣進(jìn)行了基于概率的估計。量化當(dāng)前設(shè)計的優(yōu)點(diǎn)有兩個優(yōu)點(diǎn)。首先，我們可以估計候選設(shè)計的改進(jìn)幅度。在這種情況下，我們可以避免與過度優(yōu)化合格設(shè)計有關(guān)的額外費(fèi)用。其次，我們可以估算實(shí)現(xiàn)設(shè)計目標(biāo)的成本，該設(shè)計目標(biāo)為優(yōu)化流程提供了合理的終止條件。為了提高效率，優(yōu)化方案應(yīng)加快電路仿真速度或盡可能少地調(diào)用高成本的電路仿真器。提高電路仿真效率的常用技術(shù)是將晶體管級模型替換為行為級模型。但是，基于方程或基于知識的行為模型的準(zhǔn)確性取決于問題。對于新的電路拓?fù)洌@些方法必須開發(fā)適合的數(shù)學(xué)模型，這些模型既耗時又困難，特別是在過程，電壓和溫度（PVT）變化方面。與其直接將數(shù)值優(yōu)化算法應(yīng)用于整個晶體管級響應(yīng)表面，不如將其應(yīng)用于由迭代更新的高保真仿真數(shù)據(jù)庫訓(xùn)練的替代模型，效率更高。替代模型的準(zhǔn)確性成為獲得高質(zhì)量優(yōu)化結(jié)果的關(guān)鍵。結(jié)合高斯過程模型與RRC優(yōu)化器的優(yōu)點(diǎn)，提出了一種新的優(yōu)化方案。我們進(jìn)行實(shí)驗(yàn)以將提出的技術(shù)與著名的貝葉斯優(yōu)化（BO）方法進(jìn)行比較。結(jié)果證明了該方法的有效性。開發(fā)DesignEasy軟件是為了實(shí)現(xiàn)上述功能，并提供用于電路設(shè)計自動化的通用用戶界面（UI）。

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  • 作者

    Bi, Zhaori.;

  • 作者單位

    The University of Texas at Dallas.;

  • 授予單位 The University of Texas at Dallas.;
  • 學(xué)科 Electrical engineering.
  • 學(xué)位 Ph.D.
  • 年度 2017
  • 頁碼 98 p.
  • 總頁數(shù) 98
  • 原文格式 PDF
  • 正文語種 eng
  • 中圖分類 康復(fù)醫(yī)學(xué);
  • 關(guān)鍵詞

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