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Conception et implementation d'un decodeur dedie a un modulateur Sigma-Delta.

機譯：專用于Sigma-Delta調(diào)制器的解碼器的設(shè)計和實現(xiàn)。

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Analog to Digital Converters have a considerable impact in electronic circuits. In fact, there are several types of ADCs and, according to every application; one type of ADC may be adapted better than others. Within the framework of our project intended to the detection of microfluidic substances based on a laboratory on chip platform, the SigmaDelta converters are the best choice. These SigmaDelta converters have a better precision than others and can be easily implemented. But such converters require specialized signal processing work, which can lead to a high conversion time. Thus, in this project, our goal is to reduce such conversion time in accelerating the signal processing tasks.; Basically a SigmaDelta convener is composed of two parts; the modulator and the decimator or decoder. The decoding part consists of extracting the information related to the sampled signal from the SigmaDelta modulator. Nevertheless, to carry out this part, two approaches can be chosen: (1) filtering, and (2) decoding. The decoding technique offers higher precision, but it is more complex and requires more time for data processing. The decoding technique is more adapted for our project than filtering, because sequences generated by the SigmaDelta modulator contain much more information mixed with noise thus filtering can remove a part of the requested information to restore the sampled signal. Thus, decoding is more useful in our project since high precision is our main goal.; At the same time, using a dynamic architecture in the decoder is useful to avoid redundancy in the data processing. This is advantageous for low frequency applications. The proposed architecture offers data processing acceleration from 2 to 4 times. It is based on an iterative recently published decoding algorithm.; To validate the proposed decoding algorithm, we implemented its architecture on a Field-programmable gate array (FPGA). The results show that such an approach offers an average gain of 4.00 dB for an 8-bit sequence and 1.70 dB for an 80-bit sequence.; Actel AFS-EVAL-BRD prototyping kit was used to implement the proposed architecture. This platform provides access to all FPGA Inputs/Outputs in addition to configurable clock and voltage regulators; it allows access to all FPGA functions such as the clock generator and an integrated ADC available inside this mixed-signal (analog-digital) FPGA.
機譯：模數(shù)轉(zhuǎn)換器在電子電路中具有相當(dāng)大的影響。實際上，有幾種類型的ADC，根據(jù)每種應(yīng)用，這些ADC的種類很多。一種類型的ADC可能比其他類型的ADC適應(yīng)性更好。在我們旨在基于芯片實驗室平臺的微流體物質(zhì)檢測項目的框架內(nèi)，SigmaDelta轉(zhuǎn)換器是最佳選擇。這些SigmaDelta轉(zhuǎn)換器具有比其他轉(zhuǎn)換器更高的精度，并且易于實現(xiàn)。但是這種轉(zhuǎn)換器需要專門的信號處理工作，這可能導(dǎo)致轉(zhuǎn)換時間長。因此，在本項目中，我們的目標(biāo)是減少此類轉(zhuǎn)??換時間，以加快信號處理任務(wù)。 SigmaDelta召集者基本上由兩部分組成；調(diào)制器和抽取器或解碼器。解碼部分包括從SigmaDelta調(diào)制器中提取與采樣信號有關(guān)的信息。不過，要執(zhí)行此部分，可以選擇兩種方法：（1）過濾和（2）解碼。解碼技術(shù)可提供更高的精度，但更為復(fù)雜，并且需要更多時間進(jìn)行數(shù)據(jù)處理。解碼技術(shù)比濾波更適合我們的項目，因為SigmaDelta調(diào)制器生成的序列包含更多與噪聲混合的信息，因此濾波可以刪除一部分請求的信息以恢復(fù)采樣信號。因此，由于高精度是我們的主要目標(biāo)，因此解碼在我們的項目中更加有用。同時，在解碼器中使用動態(tài)架構(gòu)可避免數(shù)據(jù)處理中的冗余。這對于低頻應(yīng)用是有利的。提出的體系結(jié)構(gòu)可將數(shù)據(jù)處理速度提高2到4倍。它基于最近發(fā)布的迭代解碼算法。為了驗證所提出的解碼算法，我們在現(xiàn)場可編程門陣列（FPGA）上實現(xiàn)了其架構(gòu)。結(jié)果表明，這種方法為8位序列提供了4.00 dB的平均增益，為80位序列提供了1.70 dB的平均增益。使用Actel AFS-EVAL-BRD原型套件來實現(xiàn)建議的體系結(jié)構(gòu)。除了可配置的時鐘和穩(wěn)壓器之外，該平臺還提供對所有FPGA輸入/輸出的訪問。它允許訪問所有FPGA功能，例如該混合信號（模擬-數(shù)字）FPGA內(nèi)部的時鐘發(fā)生器和集成ADC。

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