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Analog Integrated Circuit Design for Spike Time Dependent Encoder and Reservoir in Reservoir Computing Processors.

機(jī)譯：儲(chǔ)層計(jì)算處理器中尖峰時(shí)間相關(guān)編碼器和儲(chǔ)層的模擬集成電路設(shè)計(jì)。

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Yi, Y.;
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年度 2018
頁(yè)碼 1-73
總頁(yè)數(shù) 73
原文格式 PDF
正文語(yǔ)種 eng
中圖分類
關(guān)鍵詞
Integrated circuit design; Data representation; Reservoir Computing Processors;

機(jī)譯：集成電路設(shè)計(jì);數(shù)據(jù)表示;油藏計(jì)算處理器;

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專利

1. FPGA based spike-time dependent encoder and reservoir design in neuromorphic computing processors [J] . Yi Yang, Liao Yongbo, Wang Bin, Microprocessors and microsystems . 2016,第octa期

機(jī)譯：神經(jīng)形態(tài)計(jì)算處理器中基于FPGA的與尖峰時(shí)間相關(guān)的編碼器和存儲(chǔ)庫(kù)設(shè)計(jì)
2. Low-Loss Photonic Reservoir Computing with Multimode Photonic Integrated Circuits [J] . Andrew Katumba, Jelle Heyvaert, Bendix Schneider, Scientific reports. . 2018,第1期

機(jī)譯：采用多模光子集成電路的低損耗光子儲(chǔ)層計(jì)算
3. Analog modulation of spike-evoked transmission in CA3 circuits is determined by axonal Kv1.1 channels in a time-dependent manner [J] . Bialowas Andrzej, Rama Sylvain, Zbili Mickael, The European Journal of Neuroscience . 2015,第3a4期

機(jī)譯：CA3電路中的峰值誘發(fā)傳輸?shù)哪M調(diào)制由軸突Kv1.1通道以時(shí)間相關(guān)的方式確定
4. Analog hardware implementation of spike-based delayed feedback reservoir computing system [C] . Jialing Li, Chenyuan Zhao, Kian Hamedani, International Joint Conference on Neural Networks . 2017

機(jī)譯：基于峰值的延遲反饋儲(chǔ)層計(jì)算系統(tǒng)的模擬硬件實(shí)現(xiàn)
5. Information Representation and Computation of Spike Trains in Reservoir Computing Systems with Spiking Neurons and Analog Neurons [D] . Almassian, Amin 2016

機(jī)譯：尖峰神經(jīng)元和類比神經(jīng)元的水庫(kù)計(jì)算系統(tǒng)中峰值列車的信息表示和計(jì)算
6. Low-Loss Photonic Reservoir Computing with Multimode Photonic Integrated Circuits [O] . Andrew Katumba, Jelle Heyvaert, Bendix Schneider, -1

機(jī)譯：采用多模光子集成電路的低損耗光子儲(chǔ)層計(jì)算
7. Information Representation and Computation of Spike Trains in Reservoir Computing Systems with Spiking Neurons and Analog Neurons [O] . Almassian Amin 2016

機(jī)譯：具有尖峰神經(jīng)元和模擬神經(jīng)元的儲(chǔ)層計(jì)算系統(tǒng)中尖峰列車的信息表示和計(jì)算

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Analog Integrated Circuit Design for Spike Time Dependent Encoder and Reservoir in Reservoir Computing Processors.

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