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Network-augmented Evolvable Reconfigurable Architectures: A Novel Platform for Evolvable Hardware

機(jī)譯：網(wǎng)絡(luò)增強(qiáng)的可擴(kuò)展可重構(gòu)體系結(jié)構(gòu)：可擴(kuò)展硬件的新型平臺

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The research presented in this thesis focuses on Evolvable Hardware, a circuit design technique that relies on biologically-inspired algorithms and reconfigurable hardware to realize innovative designs. Circuits evolved with these methodologies can adapt to highly dynamic environments and are able to reconfigure themselves around faults which would permanently disable canonically-designed hardware. Furthermore, the evolutionary algorithms employed often produce hardware which a conventional, human-driven, design flow would have excluded a priori. These unconventional circuits have, in some cases, resulted in lower power consumption and higher performance with respect to their conventional counterparts.;Recently introduced platforms, directly coupling high-performance processing systems with reconfigurable logic, have considerably expanded the range of possibilities that can be attained by evolvable hardware. Exploiting one family of such platforms, a network-enabled evolvable hardware platform was developed.;Creating such a system invariably requires the development of several interconnected components, starting from the low-level architecture up to the network interconnections. The result is a novel and intuitive network-enhanced evolvable reconfigurable architecture, developed on an open-source Linux-based operating system. Aside from the network-related improvements, the platform also offers a radically different perspective into evolvable hardware, which enables effortless integration of new features and considerably reduces the effort required to create new evolvable hardware designs.;The evolutionary performance of the developed platform was evaluated on a widespread family of circuits, image filters. The development of this benchmark application enabled verification of the capabilities of the architecture as well as validation of the proposed network-based enhancements for evolvable hardware. In-depth testing, using a wide variety of different configurations, demonstrated the superior performance of the network-based evolvable hardware compared to that of conventional evolvable hardware architectures.
機(jī)譯：本文提出的研究集中在可進(jìn)化硬件上，這是一種電路設(shè)計(jì)技術(shù)，它依靠生物學(xué)啟發(fā)的算法和可重構(gòu)硬件來實(shí)現(xiàn)創(chuàng)新設(shè)計(jì)。用這些方法論發(fā)展的電路可以適應(yīng)高度動態(tài)的環(huán)境，并能夠針對故障進(jìn)行自我重新配置，而這些故障將永久禁用規(guī)范設(shè)計(jì)的硬件。此外，所采用的進(jìn)化算法通常會產(chǎn)生硬件，而傳統(tǒng)的，人工驅(qū)動的設(shè)計(jì)流程會排除先驗(yàn)因素。在某些情況下，這些非常規(guī)電路導(dǎo)致了比傳統(tǒng)電路更低的功耗和更高的性能。；最近引入的平臺，將高性能處理系統(tǒng)與可重配置邏輯直接耦合在一起，大大擴(kuò)展了可能的應(yīng)用范圍。通過可發(fā)展的硬件實(shí)現(xiàn)。利用一個這樣的平臺家族，開發(fā)了一種可網(wǎng)絡(luò)化的可進(jìn)化硬件平臺。創(chuàng)建這樣一個系統(tǒng)始終需要開發(fā)幾個互連的組件，從低級架構(gòu)到網(wǎng)絡(luò)互連。結(jié)果是在基于Linux的開源操作系統(tǒng)上開發(fā)的新穎，直觀的，網(wǎng)絡(luò)增強(qiáng)的，可演化的可重配置體系結(jié)構(gòu)。除了與網(wǎng)絡(luò)相關(guān)的改進(jìn)外，該平臺還對可演化的硬件提供了截然不同的觀點(diǎn)，從而可以輕松集成新功能，并大大減少了創(chuàng)建新的可演化硬件設(shè)計(jì)所需的工作量。評估了已開發(fā)平臺的演化性能在廣泛的電路家族中，圖像濾波器。該基準(zhǔn)應(yīng)用程序的開發(fā)使得能夠驗(yàn)證體系結(jié)構(gòu)的功能以及驗(yàn)證所提出的針對可演進(jìn)硬件的基于網(wǎng)絡(luò)的增強(qiáng)功能。使用各種不同配置進(jìn)行的深入測試證明，與傳統(tǒng)的可演化硬件體系結(jié)構(gòu)相比，基于網(wǎng)絡(luò)的可演化硬件具有優(yōu)越的性能。

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  • 作者

    Zevola, Luigi.;

  • 作者單位

    University of Illinois at Chicago.;

  • 授予單位 University of Illinois at Chicago.;
  • 學(xué)科 Electrical engineering.;Computer science.
  • 學(xué)位 M.S.
  • 年度 2017
  • 頁碼 303 p.
  • 總頁數(shù) 303
  • 原文格式 PDF
  • 正文語種 eng
  • 中圖分類 遙感技術(shù);
  • 關(guān)鍵詞

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