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首頁(yè)> 外文期刊>Circuits and Systems II: Express Briefs, IEEE Transactions on >A Real-Time Flexible Telecommunication Decoding Architecture Using FPGA Partial Reconfiguration
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A Real-Time Flexible Telecommunication Decoding Architecture Using FPGA Partial Reconfiguration

機(jī)譯：使用FPGA部分重新配置的實(shí)時(shí)靈活電信解碼架構(gòu)

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摘要

Modern telecommunication decoding schemes, leading to high computational complexity and power consumption, are weakening the feasibility of real-time applications. In this brief, a real-time reconfigurable decoding architecture is introduced to alleviate the contradiction mentioned above. The proposed architecture is partially reconfigurable on the fly so that different decoding schemes can be deployed onto merely one physical partition of reconfigurable hardware and be switched with another without significant penalty on timing and complexity. The decoding system is implemented on an FPGA evaluation board and the experiment result shows that our approach renders ple decoding schemes implemented in one system with feasibility, simplicity and power-saving ability. By adopting our architecture and the development flow, a three-LDPC-code decoder is implemented. Moreover, nearly 50% savings on hardware logic and milli-second-level real-time switching speed for decoders are both achieved.
機(jī)譯：現(xiàn)代電信解碼方案，導(dǎo)致高計(jì)算復(fù)雜性和功耗，正在削弱實(shí)時(shí)應(yīng)用的可行性。在此簡(jiǎn)述中，引入了實(shí)時(shí)可重新配置的解碼架構(gòu)以緩解上述矛盾。擬議的架構(gòu)在飛行中部分可重新配置，因此可以僅將不同的解碼方案部署到僅可重新配置硬件的一個(gè)物理分區(qū)上，并且在時(shí)間和復(fù)雜性上沒(méi)有顯著損失。解碼系統(tǒng)在FPGA評(píng)估板上實(shí)現(xiàn)，實(shí)驗(yàn)結(jié)果表明，我們的方法呈現(xiàn)在一個(gè)系統(tǒng)中實(shí)現(xiàn)的PLE解碼方案，具有可行性，簡(jiǎn)單性和節(jié)能能力。通過(guò)采用我們的架構(gòu)和開(kāi)發(fā)流，實(shí)現(xiàn)了三個(gè)LDPC代碼解碼器。此外，對(duì)解碼器的硬件邏輯和毫秒實(shí)時(shí)開(kāi)關(guān)速度近50％均已實(shí)現(xiàn)。

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