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Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications

機(jī)譯：單變量功率分析攻擊利用了用于密碼學(xué)應(yīng)用的納米CMOS VLSI電路的靜態(tài)耗散

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In this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static current of sub-50 nm CMOS integrated circuits on the internally processed data. Spice simulations of static power have been carried out to show that the coefficient of variation of nanometer logic gates is increasing with the scaling of CMOS technology. We demonstrate that it is possible to recover the secret key of a cryptographic core by exploiting this data dependence by means of different statistical distinguishers. For the first time in the literature we formulate the Attack Exploiting Static Power (AESP) as a univariate attack by using the mutual information approach to quantify the information that leaks through the static power side channel independently from the adopted leakage model. This analysis shows that countermeasures conceived to protect cryptographic hardware from attacks based on dynamic power consumption (e.g., WDDL, MDPL, SABL) still exhibit a leakage through the static power side channel. Finally, we show that the Time Enclosed Logic (TEL) concept does not leak information through the static power and is suitable to be used as a countermeasure against both attacks exploiting dynamic power and attacks exploiting static power.
機(jī)譯：在這項(xiàng)工作中，我們重點(diǎn)研究功率分析攻擊（PAA），該攻擊利用了低于50 nm CMOS集成電路的靜態(tài)電流對(duì)內(nèi)部處理數(shù)據(jù)的依賴性。已經(jīng)進(jìn)行了靜態(tài)功率的Spice仿真，以表明隨著CMOS技術(shù)的發(fā)展，納米邏輯門的變化系數(shù)正在增加。我們證明有可能通過利用不同的統(tǒng)計(jì)區(qū)分器來(lái)利用此數(shù)據(jù)依賴關(guān)系來(lái)恢復(fù)加密核心的秘密密鑰。在文獻(xiàn)中，我們首次通過使用互信息方法來(lái)量化通過靜態(tài)功率側(cè)信道泄漏的信息，而與采用的泄漏模型無(wú)關(guān)，將攻擊利用靜態(tài)功率（AESP）公式化為單變量攻擊。該分析表明，為保護(hù)加密硬件免受基于動(dòng)態(tài)功耗（例如WDDL，MDPL，SABL）的攻擊而采取的對(duì)策仍然顯示出通過靜態(tài)電源側(cè)信道的泄漏。最后，我們證明了時(shí)間封閉邏輯（TEL）概念不會(huì)通過靜態(tài)電源泄漏信息，并且適合用作針對(duì)利用動(dòng)態(tài)電源的攻擊和針對(duì)利用靜態(tài)電源的攻擊的對(duì)策。

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