摘要：
為了滿(mǎn)足無(wú)人機(jī)數(shù)據(jù)鏈對(duì)下行數(shù)據(jù)高速實(shí)時(shí)傳輸?shù)囊螅瑢?shí)現(xiàn)了一種基于PowerPC處理器和IEEE1394總線的高速數(shù)據(jù)傳輸單元。首先介紹了無(wú)人機(jī)數(shù)據(jù)鏈對(duì)下行數(shù)據(jù)傳輸設(shè)備的設(shè)計(jì)需求，其次詳細(xì)介紹了下行數(shù)據(jù)傳輸設(shè)備的系統(tǒng)結(jié)構(gòu)和數(shù)據(jù)傳輸單元的軟硬件實(shí)現(xiàn)，最后通過(guò) IEEE1394總線環(huán)繞測(cè)試的方法，驗(yàn)證了數(shù)據(jù)傳輸單元的功能和性能。驗(yàn)證結(jié)果表明：該數(shù)據(jù)傳輸單元具有設(shè)計(jì)簡(jiǎn)單、傳輸速率高、可靠性高和功耗低的特點(diǎn)，具有廣泛的應(yīng)用前景。%In order to fulfill the requirements of high-speed and real-time down data transmission of unmanned aerial vehicle data link, a high-speed data transmission unit based on PowerPC processor and IEEE1394 bus is realized. First, the paper introduces the design requirements of down data transmission system in unmanned aerial vehicle data link. Then it describes the system architecture of down data transmission system and the realization of software and hardware in data transmission unit in detail. At last, the function and performance of data transmission unit are validated through the encirclement of IEEE1394 bus. The experiment indicates that the data transmission unit has the characteristics of simple design, high transmission capability, high reliability and low power dissipation, which has broad application prospects.
摘要：
According to the protocol,IEEE1394 PHY IP mainly implements the function of bus interconnection,connection management, bus arbitration,data transmission and so on. It is a kind of digital and analog mixed SoC integrated a high-speed Serdes. As it is hard to fully verify 1394 PHY IP before the Serdes chip is designed,therefore based on introduction of the 1394 PHY IP function,put forward a kind of method to meet the need for PHY IP verification,including using GTP of Xilinx FPGA instead of Serdes,constructing FPGA pro-totype verification platform,adopting hardwire logic work along with software to make verification works. Applying the platform can veri-fy the digital logic before the Serdes is completed,greatly shortening the development time of physics layer IP. Through the test items generation,test processing monitor,test result judgment under software control,can remarkably improve the verification efficiency.%符合IEEE1394協(xié)議的物理層IP主要完成總線連接檢測(cè)、連接管理、仲裁、數(shù)據(jù)收發(fā)等功能,是一款集成高速Ser-des的數(shù)?；旌蟂oC。由于在Serdes的測(cè)試芯片設(shè)計(jì)完成前無(wú)法對(duì)1394物理層IP進(jìn)行全面驗(yàn)證,因此文中在介紹1394 PHY物理層IP各部分功能的基礎(chǔ)上,提出了一種以Xilinx的GTP代替1394物理層Serdes,構(gòu)建FPGA原型驗(yàn)證平臺(tái),采用專(zhuān)用硬件邏輯和軟件結(jié)合的方式,對(duì)1394物理層IP進(jìn)行充分驗(yàn)證的方法。使用該平臺(tái)可在Serdes設(shè)計(jì)未完成前對(duì)數(shù)字邏輯進(jìn)行驗(yàn)證,大大縮短物理層IP的開(kāi)發(fā)周期；通過(guò)軟件控制下的測(cè)試項(xiàng)生成、測(cè)試過(guò)程監(jiān)控、測(cè)試結(jié)果判斷,可顯著提高驗(yàn)證效率。
摘要：
In order to achieve the design of data collecting system in real-time, universal and miniaturization, this paper introduc-es a design and implementation of a high-speed data collecting system based on IEEE-1394 Bus. In the hardware architecture, the IEEE-1394 Bus dedicated chips are used to achieve the high-speed data acquisition and reliability transmission. By using FP-GA+DSP data processing architecture, the data acquisition and processing algorithms run separately. By using the static partial re-configuration technology, different subsystem achieves specific functional configuration. By using switch technology, the circuits of analog signals implement flexible configuration and come in pattern design. In the software architecture, a modular design con-cept is used to the system design, and switching between different operating modes is realized. The system has the strong advan-tage of data collection and solver capabilities as illustrated in the experiment.%為了實(shí)現(xiàn)數(shù)據(jù)采集系統(tǒng)實(shí)時(shí)性、通用化、小型化設(shè)計(jì)，該文提出了一種基于IEEE-1394總線的高速數(shù)據(jù)采集系統(tǒng)設(shè)計(jì)和實(shí)現(xiàn)方案。硬件架構(gòu)上，系統(tǒng)采用IEEE-1394總線專(zhuān)用芯片，實(shí)現(xiàn)了數(shù)據(jù)高速率、高可靠性傳輸；采用FPGA+DSP的數(shù)據(jù)處理架構(gòu)，將數(shù)據(jù)采集與算法處理分開(kāi)獨(dú)立運(yùn)行；采用FPGA靜態(tài)局部重構(gòu)技術(shù)，實(shí)現(xiàn)了不同子系統(tǒng)的功能配置；采用開(kāi)關(guān)動(dòng)態(tài)切換技術(shù)，實(shí)現(xiàn)了信號(hào)采集的靈活配置和小型化設(shè)計(jì)。軟件架構(gòu)上，系統(tǒng)采用模塊化設(shè)計(jì)思路，實(shí)現(xiàn)了不同工作模式之間的切換。實(shí)驗(yàn)表明該系統(tǒng)具備很強(qiáng)的數(shù)據(jù)采集與解算能力。
摘要：
With the JSF project firstly using the IEEE -1394 b bus in the aircraft ,it maked the bus widely used in the Avionics Systems .The AS5643 protocol could meet the high bandwidth ,high assurance and high reliability requirements of the new generation of flight management system by adding to the limit method on IEEE-1394 b bus protocol .This paper analysis the basic topology structre on the flight man-agement system bus and the AS 5643 agreement ,then elaborate a solution which designs and implements AS5643 protocol on the FPGA.Finally,according to the experiment validation ,the results indicate that the design solution can meet the design specifications ,have the good performance ,and also implement the ap-plication requirements of the vehicle management system bus .%隨著JSF項(xiàng)目首先在航空器中采用IEEE-1394 b總線，使得該總線在航空電子系統(tǒng)中被快速?gòu)V泛地使用。AS5643協(xié)議在IEEE-1394 b總線協(xié)議的基礎(chǔ)上通過(guò)增加限制的方法，滿(mǎn)足了新一代飛機(jī)管理系統(tǒng)總線對(duì)于高帶寬、高確定性和高可靠性的要求。分析了基于飛機(jī)管理系統(tǒng)總線的基本拓?fù)浣Y(jié)構(gòu)和AS5643協(xié)議，闡述了一種基于FPGA邏輯設(shè)計(jì)實(shí)現(xiàn)AS5643協(xié)議的解決方案。通過(guò)實(shí)驗(yàn)驗(yàn)證，表明設(shè)計(jì)解決方案滿(mǎn)足設(shè)計(jì)指標(biāo)，性能良好，實(shí)現(xiàn)了飛機(jī)管理系統(tǒng)總線機(jī)載環(huán)境的應(yīng)用要求。
摘要：
數(shù)據(jù)總線作為綜合電子系統(tǒng)的核心,它的可靠性是保證綜合電子系統(tǒng)功能有效實(shí)現(xiàn)的關(guān)鍵.針對(duì)IEEE 1394總線,研究容錯(cuò)總線結(jié)構(gòu),分別分析基于stack-tree拓?fù)涞碾p冗余以及環(huán)形冗余結(jié)構(gòu)的節(jié)點(diǎn)失效模型.其中環(huán)形冗余stack-tree的模型運(yùn)用遞歸函數(shù).使用matlab仿真計(jì)算上述模型,定量的分析比較它們的容錯(cuò)性,得出環(huán)形冗余結(jié)構(gòu)的可靠性更高,可超過(guò)0.99,且更穩(wěn)定.研究結(jié)果對(duì)1394b總線的空間應(yīng)用具有一定的參考意義.%As the core of the integrated electronics system, the reliability are keys to ensure the effective implementation of the functions of the system. The architecture of the fault-tolerant bus for IEEE 1394b is studied Failure pattern of the fault-tolerant configurations is analyzed based on stack-tree topology. Nodes failing models have been constructed, those is of 1394 dual bus and of 1394 ring bus based on the stack-tree topology, respectively. The model description of the CSTR configuration is based on recursive function. Applying the models and using Matlab, reliability measures are been evaluated, that quantitatively compares the redundant bus architectures. The results demonstrate that CSTR leads to significantly more reliability gain which is greater than 0. 99, and steadier performance. The results will provide a significant guidance for space applications of 1394b bus.
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